Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 2.00 Sep. 28, 2009 Page 174 of 870
REJ09B0429-0200
Table 7.8 DTC Execution Status
Mode
Vector Read
I
Register
Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal transfer 1 6 1 1 3
Repeat transfer 1 6 1 1 3
Block transfer 1 6 N N 3
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 7.9 Number of States Required for Each Execution Status
Object to be Accessed
On-Chip RAM
(H'FFEC00 to
H'FFEFFF)
On-Chip RAM
(On-chip RAM area
other than H'FFEC00 to
H'FFEFFF)
On-
Chip
ROM
On-Chip
I/O
Registers External Devices
Bus width 32 16 16 8 16 8 8 16 16
Access states 1 1 1 2 2 2 3 2 3
Vector read S
I
— — 1 — — 4 6 + 2m 2 3 + m Execution
status
Register
information
read/write S
J
1 — — — — — — — —
Byte data read S
K
1 1 1 2 2 2 3 + m 2 3 + m
Word data read
S
K
1 1 1 4 2 4 6 + 2m 2 3 + m
Byte data write S
L
1 1 1 2 2 2 3 + m 2 3 + m
Word data write
S
L
1 1 1 4 2 4 6 + 2m 2 3 + m
Internal operation
S
M
1 1 1 1 1 1 1 1 1
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M