Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 182 of 870
REJ09B0429-0200
Port Description
Extended Mode
(EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Feature of
I/O
Port 9 General I/O port
multiplexed with bus
control I/O, system
clock output, and
external subclock
input
P97/WAIT/CS256
P96/φ/EXCL
AS/IOS
HWR/WR
RD
P92/HBE
P91/AH
P90/LWR/LBE
P97
P96/φ/EXCL
P95
P94
P93
P92
P91
P90
Port A General I/O port
multiplexed with DTC
event counter input
and address output
PA7/EVENT7/A23
PA6/EVENT6/A22
PA5/EVENT5/A21
PA4/EVENT4/A20
PA3/EVENT3/A19
PA2/EVENT2/A18
PA1/EVENT1/A17
PA0/EVENT0/A16
PA7/EVENT7
PA6/EVENT6
PA5/EVENT5
PA4/EVENT4
PA3/EVENT3
PA2/EVENT2
PA1/EVENT1
PA0/EVENT0
Built-in input
pull-up MOS
Port B General I/O port
multiplexed with DTC
event counter input
PB7/EVENT15
PB6/EVENT14
PB5/EVENT13
PB4/EVENT12
PB3/EVENT11
PB2/EVENT10
PB1/EVENT9
PB0/EVENT8
Same as left
PC7/PWX3
PC6/PWX2
Same as left Port C General I/O port
multiplexed with
PWMX output and
IIC_2, IIC_3, and
IIC_4 I/O
PC5/SDA4
PC4/SCL4
PC3/SDA3
PC2/SCL3
PC1/SDA2
PC0/SCL2
Same as left NMOS
push-pull
output