Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxi of xl
REJ09B0429-0200
21.4.4 Procedure Program and Storable Area for Programming Data............................. 694
21.5 Protection ........................................................................................................................... 704
21.5.1 Hardware Protection ............................................................................................. 704
21.5.2 Software Protection............................................................................................... 706
21.5.3 Error Protection..................................................................................................... 706
21.6 Switching between User MAT and User Boot MAT......................................................... 708
21.7 Programmer Mode ............................................................................................................. 709
21.8 Serial Communication Interface Specification for Boot Mode.......................................... 710
21.9 Usage Notes ....................................................................................................................... 738
Section 22 Boundary Scan (JTAG)....................................................................741
22.1 Features.............................................................................................................................. 741
22.2 Input/Output Pins............................................................................................................... 743
22.3 Register Descriptions ......................................................................................................... 744
22.3.1 Instruction Register (SDIR) .................................................................................. 745
22.3.2 Bypass Register (SDBPR) .................................................................................... 746
22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 746
22.3.4 ID Code Register (SDIDR)................................................................................... 754
22.4 Operation ........................................................................................................................... 755
22.4.1 TAP Controller State Transitions.......................................................................... 755
22.4.2 JTAG Reset........................................................................................................... 756
22.5 Boundary Scan................................................................................................................... 756
22.5.1 Supported Instructions .......................................................................................... 756
22.6 Usage Notes ....................................................................................................................... 759
Section 23 Clock Pulse Generator .....................................................................763
23.1 Oscillator............................................................................................................................ 764
23.1.1 Connecting Crystal Resonator .............................................................................. 764
23.1.2 External Clock Input Method................................................................................ 765
23.2 PLL Multiplier Circuit ....................................................................................................... 766
23.3 Medium-Speed Clock Divider ........................................................................................... 766
23.4 Bus Master Clock Select Circuit........................................................................................ 766
23.5 Subclock Input Circuit ....................................................................................................... 766
23.6 Subclock Waveform Shaping Circuit................................................................................. 766
23.7 Clock Select Circuit ........................................................................................................... 767
23.8 Usage Notes ....................................................................................................................... 768
23.8.1 Note on Resonator ................................................................................................ 768
23.8.2 Notes on Board Design ......................................................................................... 768
23.8.3 Note on Operation Check...................................................................................... 768