Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 198 of 870
REJ09B0429-0200
8.5.2 Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit Bit Name Initial Value R/W Description
7 P57DR 0 R/W
6 P56DR 0 R/W
5 P55DR 0 R/W
4 P54DR 0 R/W
3 P53DR 0 R/W
2 P52DR 0 R/W
1 P51DR 0 R/W
P5DR stores output data for the port 5 pins that are
used as the general output port.
If this register is read, the P5DR values are read for
the bits with the corresponding P5DDR bits set to 1.
For the bits with the corresponding P5DDR bits
cleared to 0, the pin states are read.
0 P50DR 0 R/W
8.5.3 Pin Functions
Port 5 pins can operate as the PWMX output, SCI_1, SCI_3, and SCIF input/output, or general I/O
port pins. The relationship between register setting values and pin functions are as follows.
• P57/IRQ15/PWX1
The pin function is switched as shown below according to the combination of the OEB bit in
DACR of PWMX and the P57DDR bit.
When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ15 input pin. To use this pin as the IRQ15
input pin, clear the P57DDR bit to 0.
OEB 0 1
P57DDR 0 1 X
P57 input pin Pin function
IRQ15 input pin
P57 output pin PWX1 output pin
[Legend] X: Don't care.