Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 201 of 870
REJ09B0429-0200
• P52/IRQ10/TxD1
The pin function is switched as shown below according to the combination of the TE bit in
SCR and the SMIF bit in SCMR of SCI_1, and the P52DDR bit.
When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ10 input pin. To use as the IRQ10 input
pin, clear the P52DDR bit to 0.
TE 0 X 0 X 1
SMIF 0 1 0 1 0
P52DDR 0 1 X
P52 input pin Pin function
IRQ10 input pin
P52 output pin TxD1 output pin
[Legend] X: Don't care.
• P51/IRQ9/RxDF
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P51DDR bit.
When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ9 input pin. To use as the IRQ9 input pin,
clear the P51DDR bit to 0.
SCIF Disabled Enabled
P51DDR 0 1 X
P51 input pin Pin function
IRQ9 input pin
P51 output pin RxDF input pin
[Legend] X: Don't care.