Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 205 of 870
REJ09B0429-0200
8.6.4 Noise Canceler Enable Register (P6NCE)
P6NCE enables or disables the noise canceler circuit at port 6.
Bit Bit Name Initial Value R/W Description
7 P67NCE 0 R/W
6 P66NCE 0 R/W
5 P65NCE 0 R/W
4 P64NCE 0 R/W
3 P63NCE 0 R/W
2 P62NCE 0 R/W
1 P61NCE 0 R/W
Enables the noise canceler circuit for the
corresponding pin and the pin state is fetched into
P6DR at the sampling cycle set by NCCS.
The operation changes according to the other
control bits. See section 8.6.7, Pin Functions, for
details.
0 P60NCE 0 R/W
8.6.5 Noise Canceler Mode Control Register (P6NCMC)
P6NCMC controls whether 1 or 0 is expected for the input signal to port 6 in bit units.
Bit Bit Name Initial Value R/W Description
7 P67NCMC 0 R/W
6 P66NCMC 0 R/W
5 P65NCMC 0 R/W
4 P64NCMC 0 R/W
3 P63NCMC 0 R/W
2 P62NCMC 0 R/W
1 P61NCMC 0 R/W
1 expected: 1 is stored in the port data register
while 1 is input stably.
0 expected: 0 is stored in the port data register
while 0 is input stably.
0 P60NCMC 0 R/W