Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 208 of 870
REJ09B0429-0200
• P67/DB15
The pin function is switched as shown below according to the P67DDR bit and P67NCE bit.
P67DDR 0 1
P67NCE 0 1 X
Pin function P67 input pin DB15 input pin P67 output pin
[Legend] X: Don't care.
• P66/DB14
The pin function is switched as shown below according to the P66DDR bit and P66NCE bit.
P66DDR 0 1
P66NCE 0 1 X
Pin function P66 input pin DB14 input pin P66 output pin
[Legend] X: Don't care.
• P65/DB13/RTS
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P65DDR bit and P65NCE bit.
SCIF Disabled Enabled
P65DDR 0 1 X
P65NCE 0 1 X X
Pin function P65 input pin DB13 input pin P65 output pin RTS output pin
[Legend] X: Don't care.
• P64/DB12/CTS
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P64DDR bit and P64NCE bit.
SCIF Disabled Enabled
P64DDR 0 1 X
P64NCE 0 1 X X
Pin function P64 input pin DB12 input pin P64 output pin CTS input pin
[Legend] X: Don't care.