Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 223 of 870
REJ09B0429-0200
• P96/φ/EXCL
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P96DDR bit.
P96DDR 0 1
EXCLE 0 1 X
Pin function P96 input pin EXCL input pin φ output pin
[Legend] X: Don't care.
• P95/AS/IOS
The pin function is switched as shown below according to the operating mode and the
combination of the IOSE bit in SYSCR and the P95DDR bit.
Operating
mode
Extended mode Single-chip mode
P95DDR X 0 1
IOSE 0 1 X X
Pin function AS output pin IOS output pin P95 input pin P95 output pin
[Legend] X: Don't care.
• P94/HWR
The pin function is switched as shown below according to the operating mode and the
P94DDR bit.
Operating
mode
Extended mode Single-chip mode
P94DDR X 0 1
Pin function HWR output pin P94 input pin P94 output pin
[Legend] X: Don't care.