Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxv of xl
REJ09B0429-0200
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ............................................................................................ 2
Figure 1.2 Pin Assignment......................................................................................................... 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode) ................................................................ 21
Figure 2.2 Stack Structure in Normal Mode ............................................................................ 21
Figure 2.3 Exception Vector Table (Advanced Mode) ............................................................ 22
Figure 2.4 Stack Structure in Advanced Mode ........................................................................ 23
Figure 2.5 Memory Map .......................................................................................................... 24
Figure 2.6 CPU Registers......................................................................................................... 25
Figure 2.7 Usage of General Registers..................................................................................... 26
Figure 2.8 Stack ....................................................................................................................... 27
Figure 2.9 General Register Data Formats (1) ......................................................................... 30
Figure 2.9 General Register Data Formats (2) ......................................................................... 31
Figure 2.10 Memory Data Formats............................................................................................ 32
Figure 2.11 Instruction Formats (Examples).............................................................................. 44
Figure 2.12 Branch Address Specification in Memory Indirect Mode ...................................... 48
Figure 2.13 State Transitions ..................................................................................................... 52
Section 3 MCU Operating Modes
Figure 3.1 Address Map........................................................................................................... 61
Section 4 Exception Handling
Figure 4.1 Reset Sequence .......................................................................................................67
Figure 4.2 Stack Status after Exception Handling.................................................................... 69
Figure 4.3 Operation When SP Value is Odd .......................................................................... 70
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ................................................................... 72
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ......................................................... 81
Figure 5.3 Block Diagram of Interrupt Control Operation....................................................... 84
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in
Interrupt Control Mode 0........................................................................................ 87
Figure 5.5 State Transition in Interrupt Control Mode 1.......................................................... 88