Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 229 of 870
REJ09B0429-0200
• PA1/EVENT1/A17, PA0/EVENT0/A16
The pin function is switched as shown below according to the setting of address 13 and the
PAnDDR bit.
When using the pin as an EVENT input pin, clear the PAnDDR bit to 0. Though the settings
for the EVENT input pin have been made, set the PAnDDR bit to 1 when using the pin as the
PAn or Am output pin.
PAnDDR 0 1
Address 13 1 0
PAn input pin Pin function
EVENTn input pin
PAn output pin Am output pin
[Legend] n = 1, 0; m = 17, 16
(2) Single-Chip Mode and Address-Data Multiplex Extended Mode
Port A pins can function as the event counter input pins.
• PA7/EVENT7, PA6/EVENT6, PA5/EVENT5, PA4/EVENT4, PA3/EVENT3, PA2/EVENT2,
PA1/EVENT1, PA0/EVENT0
The pin function is switched as shown below according to the PAnDDR bit.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 to use
the pin as the PAn output pin.
PAnDDR 0 1
PAn input pin Pin function
EVENTn input pin
PAn output pin
[Legend] n = 7 to 0