Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxvi of xl
REJ09B0429-0200
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 1....................................................................................... 90
Figure 5.7 Interrupt Exception Handling ................................................................................. 92
Figure 5.8 Interrupt Control for DTC....................................................................................... 94
Figure 5.9 Conflict between Interrupt Generation and Disabling ............................................ 96
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller......................................................................... 101
Figure 6.2 IOS Signal Output Timing.................................................................................... 118
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space) ......................... 119
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ....................... 120
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space......................................................... 123
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space......................................................... 124
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ...................... 125
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ....................... 126
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access).............................. 127
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) ...................... 128
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ....................... 129
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access).............................. 130
Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0) ......................................... 131
Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0)........................................... 132
Figure 6.15 Glueless Extension Word Access (ADMXE = 0)................................................. 133
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space......................................................... 134
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space......................................................... 135
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space......................................................... 135
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) ................ 136
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access) ................ 137
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access).................. 137
Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access).................. 138
Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access) ........................ 139
Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access) ........................ 139
Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access) ................ 140
Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access).................. 141
Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access) ........................ 141
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode) .................................. 143
Figure 6.29 Example of Wait State Insertion Timing .............................................................. 145
Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ................. 146
Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ................. 147
Figure 6.32 Examples of Idle Cycle Operation........................................................................ 148