Datasheet

Section 8 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 247 of 870
REJ09B0429-0200
• PE4/LFRAME
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE4DDR bit.
LPC Disabled Enabled
PE4DDR 0 1 X
Pin function PE4 input pin PE4 output pin LFRAME input pin
[Legend] X: Don't care.
• PE3/LAD3
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE3DDR bit.
LPC Disabled Enabled
PE3DDR 0 1 X
Pin function PE3 input pin PE3 output pin LAD3 input/output pin
[Legend] X: Don't care.
• PE2/LAD2
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE2DDR bit.
LPC Disabled Enabled
PE2DDR 0 1 X
Pin function PE2 input pin PE2 output pin LAD2 input/output pin
[Legend] X: Don't care.
• PE1/LAD1
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE1DDR bit.
LPC Disabled Enabled
PE1DDR 0 1 X
Pin function PE1 input pin PE1 output pin LAD1 input/output pin
[Legend] X: Don't care.