Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxvii of xl
REJ09B0429-0200
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC......................................................................................... 152
Figure 7.2 Block Diagram of DTC Activation Source Control.............................................. 164
Figure 7.3 DTC Register Information Location in Address Space ........................................ 165
Figure 7.4 Correspondence between DTC Vector Address and Register Information........... 166
Figure 7.5 DTC Operation Flowchart .................................................................................... 167
Figure 7.6 Memory Mapping in Normal Transfer Mode ....................................................... 168
Figure 7.7 Memory Mapping in Repeat Transfer Mode ........................................................ 169
Figure 7.8 Memory Mapping in Block Transfer Mode.......................................................... 170
Figure 7.9 Chain Transfer Operation ..................................................................................... 171
Figure 7.10 DTC Operation Timing
(Example in Normal Transfer Mode or Repeat Transfer Mode)........................... 172
Figure 7.11 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ................................... 173
Figure 7.12 DTC Operation Timing (Example of Chain Transfer).......................................... 173
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit.......................................................................................... 206
Figure 8.2 Noise Canceler Operation..................................................................................... 207
Section 9 14-Bit PWM Timer (PWMX)
Figure 9.1 PWMX (D/A) Block Diagram .............................................................................. 255
Figure 9.2 PWMX (D/A) Operation....................................................................................... 263
Figure 9.3 Output Waveform (OS = 0, DADR corresponds to T
L
) ........................................ 266
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to T
H
)........................................ 267
Figure 9.5 D/A Data Register Configuration when CFS = 1.................................................. 267
Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1)............................................. 268
Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer..................................................... 272
Figure 10.2 Increment Timing with Internal Clock Source...................................................... 279
Figure 10.3 Timing of Output Compare A Output................................................................... 279
Figure 10.4 Clearing of FRC by Compare-Match A Signal..................................................... 280
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................ 280
Figure 10.6 Timing of Overflow Flag (OVF) Setting .............................................................. 281
Figure 10.7 OCRA Automatic Addition Timing...................................................................... 282
Figure 10.8 Conflict between FRC Write and Clear ................................................................ 283
Figure 10.9 Conflict between FRC Write and Increment......................................................... 284
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) .............................................. 285