Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Sep. 28, 2009 Page 284 of 870
REJ09B0429-0200
10.5.2 Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 10.9 shows the timing for this type of conflict.
φ
Address FRC address
Internal write
signal
FRC input
clock
Write data
FRC N
M
T
1
T
2
Write cycle of FRC
Figure 10.9 Conflict between FRC Write and Increment