Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxi of xl
REJ09B0429-0200
Figure 17.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)................................................................. 491
Figure 17.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1).................................................................... 492
Figure 17.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 495
Figure 17.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 495
Figure 17.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)............... 497
Figure 17.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1) ....... 499
Figure 17.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1) ....... 499
Figure 17.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)............... 500
Figure 17.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 502
Figure 17.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 503
Figure 17.23 Sample Flowchart for Slave Transmit Mode ........................................................ 504
Figure 17.24 Slave Transmit Mode Operation Timing Example (MLS = 0) ............................. 506
Figure 17.25 IRIC Setting Timing and SCL Control (1)............................................................ 507
Figure 17.26 IRIC Setting Timing and SCL Control (2)............................................................ 508
Figure 17.27 IRIC Setting Timing and SCL Control (3)............................................................ 509
Figure 17.28 Block Diagram of Noise Canceler ........................................................................ 512
Figure 17.29 Notes on Reading Master Receive Data ............................................................... 520
Figure 17.30 Flowchart for Start Condition Issuance Instruction for
Retransmission and Timing .................................................................................. 521
Figure 17.31 Stop Condition Issuance Timing........................................................................... 522
Figure 17.32 IRIC Flag Clearing Timing When WAIT = 1....................................................... 523
Figure 17.33 ICDR Register Read and ICCR Register Access Timing
in Slave Transmit Mode........................................................................................ 524
Figure 17.34 TRS Bit Set Timing in Slave Mode ...................................................................... 525
Figure 17.35 Diagram of Erroneous Operation when Arbitration Lost...................................... 527
Section 18 LPC Interface (LPC)
Figure 18.1 Block Diagram of LPC ......................................................................................... 531
Figure 18.2 Typical LFRAME Timing .................................................................................... 600
Figure 18.3 Abort Mechanism ................................................................................................. 600
Figure 18.4 SMIC Write Transfer Flow................................................................................... 601
Figure 18.5 SMIC Read Transfer Flow.................................................................................... 602
Figure 18.6 BT Write Transfer Flow........................................................................................ 603
Figure 18.7 BT Read Transfer Flow ........................................................................................ 604