Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Sep. 28, 2009 Page 289 of 870
REJ09B0429-0200
Section 11 8-Bit Timer (TMR)
This LSI has two channels of 8-bit timer modules (TMR_0 and TMR_1) which operate on the 8-
bit counter.
This LSI also has two channels of similar 8-bit timer modules (TMR_Y and TMR_X).
11.1 Features
• Selection of clock sources
⎯ TMR_0, TMR_1: The counter input clock can be selected from six internal clocks.
⎯ TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks.
• Selection of two ways to clear the counters
⎯ The counters can be cleared on compare-match A and compare-match B.
• Cascading of TMR_0 and TMR_1
(Cascading of TMR_Y and TMR_X is not allowed)
⎯ Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1
as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare
match occurrences (compare-match count mode).
• Multiple interrupt sources for each channel
⎯ TMR_0, TMR_1, TMR_Y and TMR_X: Three interrupts: Compare-match A,
compare-match B, and overflow