Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Sep. 28, 2009 Page 296 of 870
REJ09B0429-0200
Table 11.1 (2) Clock Input to TCNT and Count Condition (TMR_1)
TCR STCR
CKS2 CKS1 CKS0 ICKS1 Description
0 0 0 X Disables clock input
0 0 1 0 Increments at falling edge of internal clock φ/8
0 0 1 1 Increments at falling edge of internal clock φ/2
0 1 0 0 Increments at falling edge of internal clock φ/64
0 1 0 1 Increments at falling edge of internal clock φ/128
0 1 1 0 Increments at falling edge of internal clock φ/1024
0 1 1 1 Increments at falling edge of internal clock φ/2048
1 0 0 X Increments at compare-match A from TCNT_0*
1 0 1 X Setting prohibited
1 1 X X Setting prohibited
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should be avoided.
[Legend] X: Don't care
Table 11.1 (3) Clock Input to TCNT and Count Condition (TMR_X, TMR_Y)
TCR
Channel CKS2 CKS1 CKS0 Description
0 0 0 Disables clock input
0 0 1 Increments at falling edge of internal clock φ/4
0 1 0 Increments at falling edge of internal clock φ/256
0 1 1 Increments at falling edge of internal clock φ/2048
TMR_Y
1 X
X
Setting prohibited
0 0 0 Disables clock input
0 0 1 Increments at falling edge of internal clock φ
0 1 0 Increments at falling edge of internal clock φ/2
TMR_Y
0 1 1 Increments at falling edge of internal clock φ/4
1 X
X
Setting prohibited
[Legend] X: Don't care