Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxii of xl
REJ09B0429-0200
Figure 18.8 GA20 Output ........................................................................................................ 606
Figure 18.9 Power-Down State Termination Timing............................................................... 611
Figure 18.10 SERIRQ Timing ................................................................................................... 612
Figure 18.11 Clock Start Request Timing.................................................................................. 614
Figure 18.12 HIRQ Flowchart (Example of Channel 1) ............................................................ 618
Section 19 A/D Converter
Figure 19.1 Block Diagram of the A/D Converter................................................................... 622
Figure 19.2 Example of A/D Converter Operation
(When Channel 1 is Selected in Single Mode) ..................................................... 629
Figure 19.3 Example of A/D Converter Operation
(When Channels AN0 to AN3 are Selected in Scan Mode) ................................. 630
Figure 19.4 A/D Conversion Timing ....................................................................................... 632
Figure 19.5 Timing of External Trigger Input ......................................................................... 634
Figure 19.6 A/D Conversion Accuracy Definitions................................................................. 636
Figure 19.7 A/D Conversion Accuracy Definitions................................................................. 636
Figure 19.8 Example of Analog Input Circuit.......................................................................... 637
Figure 19.9 Example of Analog Input Protection Circuit ........................................................ 639
Figure 19.10 Analog Input Pin Equivalent Circuit..................................................................... 640
Section 21 Flash Memory
Figure 21.1 Block Diagram of Flash Memory ......................................................................... 644
Figure 21.2 Mode Transition of Flash Memory....................................................................... 645
Figure 21.3 Flash Memory Configuration................................................................................ 647
Figure 21.4 Block Division of User MAT ............................................................................... 649
Figure 21.5 Overview of User Procedure Program.................................................................. 650
Figure 21.6 System Configuration in Boot Mode .................................................................... 674
Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI............................................... 675
Figure 21.8 Overview of Boot Mode State Transition Diagram.............................................. 677
Figure 21.9 Programming/Erasing Overview Flow ................................................................. 678
Figure 21.10 RAM Map When Programming/Erasing is Executed........................................... 679
Figure 21.11 Programming Procedure ....................................................................................... 680
Figure 21.12 Erasing Procedure................................................................................................. 685
Figure 21.13 Repeating Procedure of Erasing and Programming.............................................. 687
Figure 21.14 Procedure for Programming User MAT in User Boot Mode................................ 690
Figure 21.15 Procedure for Erasing User MAT in User Boot Mode ......................................... 692
Figure 21.16 Transitions to Error-Protection State .................................................................... 707
Figure 21.17 Switching between the User MAT and User Boot MAT...................................... 708
Figure 21.18 Boot Program States ............................................................................................. 711
Figure 21.19 Bit-Rate-Adjustment Sequence............................................................................. 712