Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Sep. 28, 2009 Page 302 of 870
REJ09B0429-0200
11.3 Operation Timing
11.3.1 TCNT Count Timing
Figure 11.3 shows the TCNT count timing with an internal clock source.
φ
External clock
input pin
TCNT input
clock
TCNT N – 1 N N + 1
Figure 11.3 Count Timing for Internal Clock Input
11.3.2 Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
match, the compare-match signal is not generated until the next TCNT input clock. Figure 11.4
shows the timing of CMF flag setting.
φ
TCNT N N + 1
TCOR N
Compare-match
signal
CMF
Figure 11.4 Timing of CMF Setting at Compare-Match