Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Sep. 28, 2009 Page 306 of 870
REJ09B0429-0200
11.6 Usage Notes
11.6.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
2
state of a TCNT write cycle as shown in figure
11.7, the counter clear takes priority and the write is not performed.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 11.7 Conflict between TCNT Write and Counter Clear