Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxiii of xl
REJ09B0429-0200
Figure 21.20 Communication Protocol Format.......................................................................... 713
Figure 21.21 New Bit-Rate Selection Sequence ........................................................................ 724
Figure 21.22 Programming Sequence ........................................................................................ 728
Figure 21.23 Erasure Sequence.................................................................................................. 731
Section 22 Boundary Scan (JTAG)
Figure 22.1 JTAG Block Diagram ........................................................................................... 742
Figure 22.2 TAP Controller State Transitions.......................................................................... 755
Figure 22.3 Reset Signal Circuit Without Reset Signal Interference ....................................... 759
Figure 22.4 Serial Data Input/Output (1) ................................................................................. 760
Figure 22.5 Serial Data Input/Output (2) ................................................................................. 761
Section 23 Clock Pulse Generator
Figure 23.1 Block Diagram of Clock Pulse Generator............................................................. 763
Figure 23.2 Typical Connection to Crystal Resonator ............................................................. 764
Figure 23.3 Equivalent Circuit of Crystal Resonator ............................................................... 764
Figure 23.4 Example of External Clock Input ......................................................................... 765
Figure 23.5 Note on Board Design of Oscillation Circuit Section........................................... 768
Section 24 Power-Down Modes
Figure 24.1 Mode Transition Diagram..................................................................................... 777
Figure 24.2 Medium-Speed Mode Timing............................................................................... 780
Figure 24.3 Software Standby Mode Application Example..................................................... 782
Figure 24.4 Hardware Standby Mode Timing.......................................................................... 783
Section 26 Electrical Characteristics .................................................................817
Figure 26.1 Darlington Transistor Drive Circuit (Example) .................................................... 821
Figure 26.2 LED Drive Circuit (Example)............................................................................... 822
Figure 26.3 Output Load Circuit.............................................................................................. 822
Figure 26.4 System Clock Timing ........................................................................................... 824
Figure 26.5 Oscillation Stabilization Timing ........................................................................... 824
Figure 26.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) .................... 825
Figure 26.7 External Clock Input Timing ................................................................................ 825
Figure 26.8 Timing of External Clock Output Stabilization Delay Time ................................ 826
Figure 26.9 Subclock Input Timing ......................................................................................... 826
Figure 26.10 Reset Input Timing ............................................................................................... 827
Figure 26.11 Interrupt Input Timing .......................................................................................... 828
Figure 26.12 Basic Bus Timing/2-State Access......................................................................... 830
Figure 26.13 Basic Bus Timing/3-State Access......................................................................... 831
Figure 26.14 Basic Bus Timing/3-State Access with One Wait State........................................ 832