Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxiv of xl
REJ09B0429-0200
Figure 26.15 Even Byte Access (ADMXE = 0)......................................................................... 833
Figure 26.16 Odd Byte Access (ADMXE = 0) .......................................................................... 834
Figure 26.17 Word Access (ADMXE = 0) ................................................................................ 835
Figure 26.18 Burst ROM Access Timing/2-State Access.......................................................... 836
Figure 26.19 Burst ROM Access Timing/1-State Access.......................................................... 837
Figure 26.20 Multiplex Bus Timing/Data 2-State Access.......................................................... 839
Figure 26.21 Multiplex Bus Timing/Data 3-State Access.......................................................... 840
Figure 26.22 I/O Port Input/Output Timing ............................................................................... 842
Figure 26.23 PWMX Output Timing ......................................................................................... 842
Figure 26.24 SCK Clock Input Timing...................................................................................... 842
Figure 26.25 SCI Input/Output Timing (Clock Synchronous Mode)......................................... 842
Figure 26.26 A/D Converter External Trigger Input Timing..................................................... 843
Figure 26.27 WDT Output Timing (RESO)............................................................................... 843
Figure 26.28 I
2
C Bus Interface Input/Output Timing................................................................. 845
Figure 26.29 LPC Interface (LPC) Timing ................................................................................ 846
Figure 26.30 JTAG ETCK Timing ............................................................................................ 847
Figure 26.31 Reset Hold Timing................................................................................................ 848
Figure 26.32 JTAG Input/Output Timing .................................................................................. 848
Figure 26.33 Connecting Capacitors to VCC and VCL Pins ..................................................... 851
Appendix
Figure C.1 Package Dimensions (TQFP-144) ........................................................................ 855