Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxv of xl
REJ09B0429-0200
Tables
Section 1 Overview
Table 1.1 Pin Assignment in Each Operating Mode................................................................. 4
Table 1.2 Pin Functions .......................................................................................................... 10
Section 2 CPU
Table 2.1 Instruction Classification ........................................................................................ 33
Table 2.2 Operation Notation ................................................................................................. 34
Table 2.3 Data Transfer Instructions....................................................................................... 35
Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 36
Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 37
Table 2.5 Logic Operations Instructions................................................................................. 38
Table 2.6 Shift Instructions..................................................................................................... 38
Table 2.7 Bit Manipulation Instructions (1)............................................................................ 39
Table 2.7 Bit Manipulation Instructions (2)............................................................................ 40
Table 2.8 Branch Instructions................................................................................................. 41
Table 2.9 System Control Instructions.................................................................................... 42
Table 2.10 Block Data Transfer Instructions............................................................................ 43
Table 2.11 Addressing Modes .................................................................................................. 45
Table 2.12 Absolute Address Access Ranges........................................................................... 47
Table 2.13 Effective Address Calculation (1)........................................................................... 49
Table 2.13 Effective Address Calculation (2)........................................................................... 50
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection ............................................................................ 55
Section 4 Exception Handling
Table 4.1 Exception Types and Priority.................................................................................. 63
Table 4.2 Exception Handling Vector Table........................................................................... 64
Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 68
Section 5 Interrupt Controller
Table 5.1 Pin Configuration.................................................................................................... 72
Table 5.2 Correspondence between Interrupt Source and ICR............................................... 74
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 82
Table 5.4 Interrupt Control Modes ......................................................................................... 84
Table 5.5 Interrupts Selected in Each Interrupt Control Mode............................................... 85