Datasheet

Section 13 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 28, 2009 Page 329 of 870
REJ09B0429-0200
Figure 13.1 is a block diagram of SCI_1 and SCI_3.
RxD1/RxD3
TxD1/TxD3
SCK1/SCK3
Clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
RDR
TSRRSR
Parity generation
Parity check
[Legend]
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
TDR
Bus interface
Internal data bus
External clock
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
Figure 13.1 Block Diagram of SCI_1 and SCI_3