Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxvii of xl

REJ09B0429-0200

Table 8.3 Port 2 Input Pull-Up MOS States.......................................................................... 190

Table 8.4 Port 3 Input Pull-Up MOS States.......................................................................... 193

Table 8.5 Port 6 Input Pull-Up MOS States.......................................................................... 210

Table 8.6 Input Pull-Up MOS States .................................................................................... 230

Table 8.7 Port D Input Pull-Up MOS States......................................................................... 243

Section 9 14-Bit PWM Timer (PWMX)

Table 9.1 Pin Configuration.................................................................................................. 256

Table 9.2 Clock Select of PWMX_1 and PWMX_0 ............................................................ 261

Table 9.3 Settings and Operation (Examples when φ = 34 MHz)......................................... 264

Table 9.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 269

Section 10 16-Bit Free-Running Timer (FRT)

Table 10.1 FRT Interrupt Sources .......................................................................................... 282

Table 10.2 Switching of Internal Clock and FRC Operation.................................................. 287

Section 11 8-Bit Timer (TMR)

Table 11.1 (1) Clock Input to TCNT and Count Condition (TMR_0)...................................... 295

Table 11.1 (2) Clock Input to TCNT and Count Condition (TMR_1)...................................... 296

Table 11.1 (3) Clock Input to TCNT and Count Condition (TMR_X, TMR_Y) ..................... 296

Table 11.2 Registers Accessible by TMR_X/TMR_Y ........................................................... 301

Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 305

Table 11.4 Switching of Internal Clocks and TCNT Operation.............................................. 309

Section 12 Watchdog Timer (WDT)

Table 12.1 Pin Configuration.................................................................................................. 313

Table 12.2 WDT Interrupt Source .......................................................................................... 322

Section 13 Serial Communication Interface (SCI)

Table 13.1 Pin Configuration.................................................................................................. 330

Table 13.2 Relationships between N Setting in BRR and Bit Rate B..................................... 343

Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)............ 344

Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 344

Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 344

Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)......................... 345

Table 13.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........ 346

Table 13.8 BRR Settings for Various Bit Rates

(Smart Card Interface Mode, n = 0, s = 372) ........................................................ 346

Table 13.9 Maximum Bit Rate for Each Frequency

(Smart Card Interface Mode, S = 372).................................................................. 346