Datasheet

Rev. 2.00 Sep. 28, 2009 Page xl of xl

REJ09B0429-0200

Table 22.2 JTAG Register Serial Transfer ............................................................................. 744

Table 22.3 Correspondence between Pins and Boundary Scan Register ................................ 747

Section 23 Clock Pulse Generator

Table 23.1 Damping Resistance Values ................................................................................. 764

Table 23.2 Crystal Resonator Parameters............................................................................... 765

Table 23.3 Ranges of Multiplied Clock Frequency ................................................................ 766

Section 24 Power-Down Modes

Table 24.1 Operating Frequency and Wait Time.................................................................... 772

Table 24.2 LSI Internal States in Each Mode ......................................................................... 778

Section 26 Electrical Characteristics

Table 26.1 Absolute Maximum Ratings ................................................................................. 817

Table 26.2 DC Characteristics (1) .......................................................................................... 818

Table 26.2 DC Characteristics (2) .......................................................................................... 820

Table 26.3 Permissible Output Currents................................................................................. 821

Table 26.4 Clock Timing........................................................................................................ 823

Table 26.5 External Clock Input Conditions .......................................................................... 823

Table 26.6 Subclock Input Conditions.................................................................................... 824

Table 26.7 Control Signal Timing .......................................................................................... 827

Table 26.8 Bus Timing ........................................................................................................... 829

Table 26.9 Multiplex Bus Timing........................................................................................... 838

Table 26.10 Timing of On-Chip Peripheral Modules ............................................................... 841

Table 26.11 I

C Bus Timing ..................................................................................................... 844

Table 26.12 LPC Module Timing............................................................................................. 845

Table 26.13 JTAG Timing........................................................................................................ 847

Table 26.14 A/D Conversion Characteristics

(AN7 to AN0 Input: 80/160-State Conversion).................................................... 849

Table 26.15 Flash Memory Characteristics .............................................................................. 850

Appendix

Table A.1 I/O Port States in Each Processing State............................................................... 853