Datasheet

Section 1 Overview
Rev. 2.00 Sep. 28, 2009 Page 2 of 870
REJ09B0429-0200
• Reprograming count: 1000 times (Typ.)
• General I/O ports
I/O pins: 107
Input-only pins: 9
• Supports various power-down states
• Compact package
Package (code) Body Size Pin Pitch
PTQP0144LC-A 16.0 × 16.0 mm 0.4 mm
1.2 Block Diagram
ROM
(
Flash)
512K
(+16K UB)
EVC
H8S/2600 CPU
DTC
Clock pulse
generator
RAM
40K
LPC
14-bit PWM ×
4
WDT × 2
Port
1
Port
2
Port
3
Port
4
Port
5
Port
6
Port
7
Port
E
Port
F
Port
D
Port
C
Port
B
Port
A
P
ort
9
P
ort
8
A/D converter
TMR
Interru
pt
controller
JT
AG
SCI_1, SCI_3
SCIF
FRT
C
RC calculator
IIC_0 to IIC_5
[Legend]
CPU: Central processing unit
DTC: Data transfer controller
EVC: Event counter
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
FRT: 16-bit free running timer
IIC: I
2
C bus interface
LPC: LPC interface
WDT: Watchdog timer
JTAG: Boundary scan
TMR: 8-bit timer
Bus contro
ller
Figure 1.1 Internal Block Diagram