Datasheet

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 28, 2009 Page 409 of 870
REJ09B0429-0200
15.3.1 Receive Shift Register (FRSR)
FRSR is a register that receives data and converts serial data input from the RxDF pin to parallel
data. It stores the data in the order received from the LSB (bit 0). When one frame of serial data
has been received, the data is transferred to FRBR.
FRSR cannot be read from the CPU/LPC interface.
15.3.2 Receive Buffer Register (FRBR)
FRBR is an 8-bit read-only register that stores received serial data. It can read data correctly when
the DR bit in FLSR is set.
When the FIFO is disabled, the data in FRBR must be read before the next data is received. If new
data is received before the remaining data is read, the data is overwritten, resulting in an overrun
error.
When this register is read with the FIFO enabled, the first buffer of the receive FIFO is read.
When the receive FIFO becomes full, the subsequent receive data is lost, resulting in an overrun
error.
Bit Bit Name Initial Value R/W Description
7 to 0 Bit 7 to
bit 0
All 0 R Stores received serial data.
The data is 16 bytes when the FIFO is enabled.
15.3.3 Transmitter Shift Register (FTSR)
FTSR is a register that converts parallel data from the TxDF pin to serial data and then transmits
the serial data. When one frame transmission of serial data is completed, the next data is
transferred from FTHR. The serial data is transmitted from the LSB (bit 0).
FTSR cannot be written from the H8S CPU/LPC interface.