Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 457 of 870
REJ09B0429-0200
17.3.4 I
2
C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name
Initial
Value
R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
2
C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
This bit is valid only in master mode with the I
2
C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8th
clock), the IRIC flag is set to 1 in ICCR, and a wait state
begins (with SCL at the low level). When the IRIC flag
is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
For details, refer to section 17.4.7, IRIC Setting Timing
and SCL Control.
5
4
3
CKS2
CKS1
CKS0
All 0 R/W Transfer Clock Select
These bits are used only in master mode.
These bits select the required transfer clock rate, together
with bits IICX5 (channel 5), IICX4 (channel 4), and IICX3
(channel 3) in the IICX3 register and bits IICX2 (channel
2), IICX1 (channel 1), and IICX0 (channel 0) in the STCR
register. Refer to table 17.3.