Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 479 of 870
REJ09B0429-0200
17.3.9 I
2
C SMBus Control Register (ICSMBCR)
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support
the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to
1000 ns. Table 17.6 shows the relationship between the ICSMBCR setting and output data hold
time.
When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled
to access when bit MSTP4 is cleared to 0.
Bit Bit Name
Initial
Value
R/W Description
7
6
5
4
3
2
SMB5E
SMB4E
SMB3E
SMB2E
SMB1E
SMB0E
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
SMBus Enable
These bits enable/disable to support the SMBus, in
combination with bits FSEL1 and FSEL0. Bits SMB5E,
SMB4E, SMB3E, SMB2E, SMB1E, and SMB0E control
IIC_5, IIC_4, IIC_3, IIC_2, IIC_1, and IIC_0, respectively.
0: Disables to support the SMBus
1: Enables to support the SMBus
1
0
FSEL1
FSEL0
0
0
R/W
R/W
Frequency Selection
These bits must be specified to match the system clock
frequency in order to support the SMBus. For details of the
setting, see table 17.7.