Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 495 of 870
REJ09B0429-0200
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
IRTR
ICDR
SCL
(master output)
Data 1
[1] TRS cleared to 0
IRIC clear to 0
[6] IRIC clear
[5] ICDR read
(Data 1)
[6] IRIC clear
(to end wait insertion)
User processing
Bit 5 Bit 4 Bit 3
5439
Data 1 Data 2
[3] [3]
A
[2] ICDR read
(dummy read)
Master transmit mode Master receive mode
A
[4]IRTR=0
[4] IRTR=1
Figure 17.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1)
SDA
(master output)
SDA
(slave output)
21
4
3
65
8
7
998
A
A
Bit 7Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRIC
IRTR
ICDR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[6] IRIC clear
(to end wait
insertion)
[8] Wait for one clock pulse
[11] IRIC clear
[14] IRIC clear
(to end wait
insertion)
[16] ICDR read
(Data 3)
User processing
[12]
[3]
[10] ICDR read (Data 2)
[9]
Set TRS=1
[7] Set ACKB=1
[15] WAIT cleared to 0,
IRIC clear
[17] Stop condition issuance
Bit 0
Stop condition generation
[13] IRTR=1
[13] IRTR=0
[12]
[4] IRTR=1
[4] IRTR=0
[3]
Figure 17.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)