Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 520 of 870
REJ09B0429-0200
SDA
SCL
Internal clock
BBSY bit
Master receive mode
ICDR read
disabled period
Bit 0
A
8
9
Stop condition
(a)
Start condition
Execution of instruction
for issuing stop condition
(write 0 to BBSY and SCP)
Confirmation of stop
condition issuance
(read BBSY = 0)
Start condition
issuance
Figure 17.29 Notes on Reading Master Receive Data
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.