Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 523 of 870
REJ09B0429-0200
SCL
IRIC
[1] SCL = low determination
VIH
[2] IRIC clear
SDA
Secures a high period
SCL = low detected
Figure 17.32 IRIC Flag Clearing Timing When WAIT = 1
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
11. Note on ICDR register read and ICCR register access in slave transmit mode
In I
2
C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
during the time shaded in figure 17.33. However, such read and write operations source no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
⎯ Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
⎯ Monitor the BC2 to BC0 counter in ICMR; when the count is B'000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.