Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 545 of 870
REJ09B0429-0200
R/W
Bit Bit Name
Initial
Value
Slave Host Description
2 IBFIE2 0 R/W ⎯ IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled
1 IBFIE1 0 R/W ⎯ IDR1 Receive Complete interrupt Enable
Enables or disables IBFI1 interrupt to the slave (this
LSI).
0: Input data register (IDR1) receive complete
interrupt requests disabled
1: Input data register (IDR1) receive complete
interrupt requests enabled
0 ERRIE 0 R/W ⎯ Error Interrupt Enable
Enables or disables ERRI interrupt to the slave (this
LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note: * Only 0 can be written to bits 6 to 4, to clear the flag.