Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 546 of 870
REJ09B0429-0200
• HICR3
R/W
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined R ⎯ 0: LFRAME Pin state is low level
1: LFRAME Pin state is high level
6 CLKRUN Undefined R ⎯ 0: CLKRUN Pin state is low level
1: CLKRUN Pin state is high level
5 SERIRQ Undefined R ⎯ 0: SERIRQ Pin state is low level
1: SERIRQ Pin state is high level
4 LRESET Undefined R ⎯ 0: LRESET Pin state is low level
1: LRESET Pin state is high level
3 LPCPD Undefined R ⎯ 0: LPCPD Pin state is low level
1: LPCPD Pin state is high level
2 PME Undefined R ⎯ 0: PME Pin state is low level
1: PME Pin state is high level
1 LSMI Undefined R ⎯ 0: LSMI Pin state is low level
1: LSMI Pin state is high level
0 LSCI Undefined R ⎯ 0: LSCI Pin state is low level
1: LSCI Pin state is high level
18.3.3 Host Interface Control Register 4 (HICR4)
HICR4 controls the operation of the KCS, SMIC, and BT interface functions on channel 3.
R/W
Bit Bit Name Initial Value Slave Host Description
7 LADR12SEL 0 R/W ⎯ Switches the channel accessed via LADR12H and
LADR12L.
0: LADR1 is selected
1: LADR2 is selected
6 to 4 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be changed.