Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 548 of 870
REJ09B0429-0200
18.3.4 Host Interface Control Register 5 (HICR5)
HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts.
R/W
Bit Bit Name
Initial
Value Slave Host
Description
7 to 2 ⎯ All 0 R/W ⎯ Reserved
The initial value bit should not be changed.
1 SCIFE 0 R/W ⎯ SCIF Enable
Enables or disables access from the LPC host of
the SCIF.
0: Disables access to the SCIF from the LPC host
1: Enables access to the SCIF from the LPC host
0 ⎯ 0 R/W ⎯ Reserved
The initial value should not be changed.
18.3.5 Pin Function Control Register (PINFNCR)
PINFNCR selects whether the pins of the associated port are used for the LPC function or general
I/O.
R/W
Bit Bit Name
Initial
Value Slave Host
Description
7 to 3 ⎯ All 0 R/W ⎯ Reserved
The initial value bit should not be changed.
2 SERIRQOFF 0 R/W ⎯ 0: SERIRQ pin
1: General I/O port
1 LPCPDOFF 0 R/W ⎯ 0: LPCPD pin
1: General I/O port
0 CLKRUNOFF 0 R/W ⎯ 0: CLKRUN pin
1: General I/O port