Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 549 of 870
REJ09B0429-0200
18.3.6 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 18.2 shows the initial value of each register. Table 18.3 shows the host register selection in
address match determination. Table 18.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 18.2 LADR1, LADR2 Initial Values
Register Name Initial Value Description
LADR1 H'0060 I/O address of channel 1
LADR2 H'0062 I/O address of channel 2