Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 561 of 870
REJ09B0429-0200
R/W
Bit Bit Name Initial Value Slave Host Description
3 C/D3 0 R R Command/Data Flag
When the host writes to IDR3, bit 2 of the I/O
address is written into this bit to indicate whether
IDR3 contains data or a command.
0: Content of input data register (IDR3) is a data
1: Content of input data register (IDR3) is a
command
2 DBU32 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF3A 0 R R Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This is an internal interrupt source to the
slave (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host writes to IDR3 in an I/O write cycle
0 OBF3A 0 R/(W)* R Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not transmit data in ODR3
[Clearing conditions]
• When the host reads ODR3 in an I/O read cycle
• When the slave writes 0 to bit OBF3A
1: There is transmit data in ODR3
[Setting condition]
• When the slave writes to ODR3
Note: * Only 0 can be written to clear the flag.