Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 573 of 870
REJ09B0429-0200
18.3.15 SERIRQ Control Register 3 (SIRQCR3)
SIRQCR3 selects the SERIRQ interrupt requests of the SCIF.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 to 4 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be changed.
3
2
1
0
SCSIRQ3
SCSIRQ2
SCSIRQ1
SCSIRQ0
0
0
0
0
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
SCIF SERIRQ Interrupt Select
These bits select the SCIF interrupt request to the
host.
0000: No interrupt request to the host
0001: HIRQ1
0010: SMI
0011: HIRQ3
0100: HIRQ4
0101: HIRQ5
0110: HIRQ6
0111: HIRQ7
1000: HIRQ8
1001: HIRQ9
1010: HIRQ10
1011: HIRQ11
1100: HIRQ12
1101: HIRQ13
1110: HIRQ14
1111: HIRQ15