Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 575 of 870
REJ09B0429-0200
18.3.17 SERIRQ Control Register 5 (SIRQCR5)
SIRQCR5 selects the output of the host interrupt request signal of each frame.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7
6
5
4
3
2
1
0
SELIRQ15
SELIRQ14
SELIRQ13
SELIRQ8
SELIRQ7
SELIRQ5
SELIRQ4
SELIRQ3
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SERIRQ Output Select
These bits select the state of the output on the pin for
LPC host interrupt requests (HIRQ15, HIRQ14,
HIRQ13, HIRQ8, HIRQ7, HIRQ5, HIRQ4, and
HIRQ3).
0: [When host interrupt request is cleared]
SERIRQ pin output is in the Hi-Z state
[When host interrupt request is set]
SERIRQ pin output is low
1: [When host interrupt request is cleared]
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.