Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 600 of 870
REJ09B0429-0200
ADDRStart
LFRAME
LAD3 to
LAD0
Number of clocks
LCLK
TAR Sync Data TAR Start
Cycle type,
direction,
and size
114 12221
Figure 18.2 Typical LFRAME Timing
ADDRStart
LFRAME
LAD3 to LAD0
LCLK
TAR Sync
Cycle type,
direction,
and size
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 18.3 Abort Mechanism
18.4.3 SMIC Mode Transfer Flow
Figure 18.4 shows the write transfer flow and figure 18.5 shows the read transfer flow in SMIC
mode.