Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 618 of 870
REJ09B0429-0200
Table 18.13 HIRQ Setting and Clearing Conditions when SCIF Channels are Used
Host Interrupt Setting Condition Clearing Condition
SMI
HIRQi
(i = 1, 3 to 15)
The SCIF interrupt corresponding to the
host interrupt request selected by
SIRQCR3 occurs.
Relevant SCIF interrupt is cleared
Slave CPU Master CPU
ODR1 write
Write 1 to IRQ1E1
OBF1 = 0?
Yes
No
No
Yes
All bytes
transferred?
SERIRQ IRQ1 output
SERIRQ IRQ1
source clear
Interrupt initiation
ODR1 read
Hardware operation
Software operation
Figure 18.12 HIRQ Flowchart (Example of Channel 1)