Datasheet

Section 18 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 619 of 870
REJ09B0429-0200
18.6 Usage Note
18.6.1 Data Conflict
The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but
an interface protocol that uses the flags in STR must be followed to avoid data conflict. For
example, if the host and slave both try to access IDR or ODR at the same time, the data will be
corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to
data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to
TWR15 has been obtained.
Table 18.14 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.