Datasheet

Section 19 A/D Converter
Rev. 2.00 Sep. 28, 2009 Page 631 of 870
REJ09B0429-0200
19.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) has passed after the ADST bit in ADCSR is
set to 1, then starts A/D conversion. Figure 19.4 shows the A/D conversion timing. Tables 19.3
and 19.4 show the A/D conversion time.
As indicated in figure 19.4, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 19.3.
In scan mode, the values given in table 19.3 apply to the first conversion time. The values given in
table 19.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.