Datasheet

Section 19 A/D Converter
Rev. 2.00 Sep. 28, 2009 Page 632 of 870
REJ09B0429-0200
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
(2)
(1)
t
D
t
SPL
t
CONV
Figure 19.4 A/D Conversion Timing