Datasheet

Section 23 Clock Pulse Generator
Rev. 2.00 Sep. 28, 2009 Page 766 of 870
REJ09B0429-0200
23.2 PLL Multiplier Circuit
The PLL multiplier circuit generates a clock of 4 times the frequency of its input clock. The
frequency range of the multiplied clock is shown in table 23.3.
Table 23.3 Ranges of Multiplied Clock Frequency
Input Clock (MHz) Multiplier System Clock (MHz)
Crystal Resonator, 5 to 8.5 4 20 to 34
External Clock
23.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16,
and φ/32 clocks.
23.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in
SBYCR.
23.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
When the subclock is not used, subclock input should not be enabled.
23.6 Subclock Waveform Shaping Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.