Datasheet

Section 24 Power-Down Modes
Rev. 2.00 Sep. 28, 2009 Page 772 of 870
REJ09B0429-0200
Table 24.1 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time 20MHz 25MHz 34MHz Unit
0 0 0 8192 states 0.4 0.3 0.2
0 0 1 16384 states 0.8 0.7 0.5
0 1 0 32768 states 1.6 1.3 1.0
0 1 1 65536 states 3.3 2.6 1.9
1 0 0 131072 states 6.6 5.2 3.9
1 0 1 262144 states 13.1 10.5 7.7
ms
1 1 X Reserved* ⎯ ⎯ ⎯
Recommended specification
Note: * Setting prohibited.
[Legend] X: Don't care
24.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit Bit Name
Initial
Value
R/W Description
7, 6 ⎯ 0 R/W Reserved
The initial value should not be changed.
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB) input
from the EXCL pin is sampled using the clock (φ)
generated by the system clock pulse generator.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
4 EXCLE 0 R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3 ⎯ 0 R/W Reserved
The initial value should not be changed.