Datasheet

Section 25 List of Registers
Rev. 2.00 Sep. 28, 2009 Page 786 of 870
REJ09B0429-0200
25.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of
access states indicates the number of states based on the specified reference clock.
Note: Access to undefined or reserved addresses is prohibited. Since operation or continued
operation is not guaranteed when these registers are accessed, do not attempt such access.
Register Name Abbreviation
Number
of Bits Address Module
Data
Bus
Width
Number
of Access
States
Receive buffer register FRBR 8 H'FC80 SCIF 16 2
Transmitter holding register FTHR 8 H'FC80 SCIF 16 2
Divisor latch L FDLL 8 H'FC80 SCIF 16 2
Interrupt enable register FIER 8 H'FC81 SCIF 16 2
Divisor latch H FDLH 8 H'FC81 SCIF 16 2
Interrupt identification register FIIR 8 H'FC82 SCIF 16 2
FIFO control register FFCR 8 H'FC82 SCIF 16 2
Line control register FLCR 8 H'FC83 SCIF 16 2
Modem control register FMCR 8 H'FC84 SCIF 16 2
Line status register FLSR 8 H'FC85 SCIF 16 2
Modem status register FMSR 8 H'FC86 SCIF 16 2
Scratch pad register FSCR 8 H'FC87 SCIF 16 2
SCIF control register SCIFCR 8 H'FC88 SCIF 16 2
Host interface control register 4 HICR4 8 H'FD00 LPC 16 2
BT status register 0 BTSR0 8 H'FD02 LPC 16 2
BT status register 1 BTSR1 8 H'FD03 LPC 16 2
BT control/status register 0 BTCSR0 8 H'FD04 LPC 16 2
BT control/status register 1 BTCSR1 8 H'FD05 LPC 16 2
BT control register BTCR 8 H'FD06 LPC 16 2
BT interrupt mask register BTIMSR 8 H'FD07 LPC 16 2
SMIC flag register SMICFLG 8 H'FD08 LPC 16 2
Host interface control register 5 HICR5 8 H'FD09 LPC 16 2
SMIC control/status register SMICCSR 8 H'FD0A LPC 16 2
SMIC data register SMICDTR 8 H'FD0B LPC 16 2