Datasheet

Section 26 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 823 of 870
REJ09B0429-0200
Table 26.4 Clock Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit Reference
Clock cycle time t
cyc
29.4 50 ns
Clock high level pulse
width
t
CH
9.7 ⎯
Clock low level pulse width t
CL
9.7 ⎯
Clock rise time t
Cr
⎯ 5
Clock fall time t
Cf
⎯ 5
Figure 26.4
Reset oscillation
stabilization (crystal)
t
OSC1
10 ⎯ ms Figure 26.5
Software standby
oscillation stabilization time
(crystal)
t
OSC2
8 ⎯ Figure 26.6
Table 26.5 External Clock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit
Test
Conditions
External clock input low level
pulse width
t
EXL
58.8 ⎯ ns
External clock input high level
pulse width
t
EXH
58.8 ⎯ ns
External clock input rising time t
EXr
⎯ 5 ns
External clock input falling time t
EXf
⎯ 5 ns
Figure 26.7
Clock low level pulse width t
CL
0.4 0.6 t
cyc
Clock high level pulse width t
CH
0.4 0.6 t
cyc
Figure 26.4
External clock output
stabilization delay time
t
DEXT
* 500 ⎯ μs Figure 26.8
Note: * t
DEXT
includes a RES pulse width (t
RESW
).