Datasheet

Section 26 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 824 of 870
REJ09B0429-0200
Table 26.6 Subclock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Typ. Max. Unit
Measureme
nt Condition
Subclock input low level pulse
width
t
EXCLL
⎯ 15.26 ⎯ μs
Subclock input high level pulse
width
t
EXCLH
⎯ 15.26 ⎯ μs
Subclock input rising time t
EXCLr
⎯ ⎯ 10 ns
Subclock input falling time t
EXCLf
⎯ ⎯ 10 ns
Figure 26.9
Clock low level pulse width t
CL
0.4 ⎯ 0.6 t
cyc
Figure 26.4
Clock high level pulse width t
CH
0.4 ⎯ 0.6 t
cyc
t
Cr
t
CL
t
Cf
t
cyc
t
CH
φ
Figure 26.4 System Clock Timing
t
OSC1
t
OSC1
VCC
STBY
RES
φ
Figure 26.5 Oscillation Stabilization Timing